1. Field of the Invention
The present invention relates generally to a receiver and more particularly to a current mode interface receiver with process insensitive common mode current extraction and the method, which may be applied in a MPL communication system.
2. Description of the Related Art
The constraints of interconnect standard in small handheld electronic devices are severe. Today's cellular handsets and PDAs demand lower power, lower number of wires and lower Electromagnetic Interference (EMI). Mobile Pixel Link (MPL), compared to the existing interface such as LVDS and RSDS, provides an optimized interface between video ports on sources and targets. Its three main attributes are: fewer wires (2 active lines), low power, and very low EMI.
To gain its benefits of low power and low EMI, MPL uses small-magnitude current signaling transmission. The two logic states are determined by the magnitude of the current that is sourced from the receiver to the transmitter. The two currents can be thought of as an AC current riding on a DC bias current. Typically the two currents are 150 μA and 450 μA and considered to be ±150 μA riding on a constant 300 μA.
MPL defines the high current (i.e. 450 μA) as a Logic Low and the low current (i.e. 150 μA) as the Logic High with reference to a DC component of 300 μA. However, due to the chip to chip process variation during the semiconductor fabrication, a first current reference Icom obtained from a first BandGap reference circuit at the transmitter may differ from a second current reference Icom+Idiff obtained from a second BandGap reference circuit at the receiver, compared to the low small-magnitude current, wherein Idiff is a delta current due to the chip to chip process variation during the semiconductor fabrication. The inconsistence between the first and the second current references will cause a wrong signal interpretation at the receiver.
In FIG. 1, a block diagram illustrates a conventional data communication system, e.g. a MPL, featuring a first BandGap reference circuit 21 and a second BandGap reference circuit 31, locating at the transmitter and the receiver, respectively.
As shown in FIG. 1, at the transmitter, a transmitting system 10 is coupled to a plurality of current mode drivers 22-24 and provides an input signal to each of current mode drivers 22-24. The first BandGap reference circuit 21 is coupled to each of the plurality of current mode drivers 22-24 and provides a first current reference Icom. Each of the current mode drivers 22-24 compares the first current reference Icom with the corresponding input signal from the transmitting system 10 and generates an output signal to a signal channel, respectively. Specifically, the signal channels, connecting the transmitter and the receiver, are clock and data channels. Each of the output signals from the transmitter is coupled to the corresponding current mode sink 32-34 at the receiver as an input signal. The second BandGap reference circuit 31 is coupled to a plurality of current mode sinks 32-34 and provides a second current reference Icom+Idiff. Each of the current mode sinks 32-34 compares the second current reference Icom+Idiff with the input signal from the corresponding current mode driver 22-24 and generates an output signal to a receiving system 40, respectively.
The second current reference Icom+Idiff is expected to be identical to the first current reference Icom in order to properly interpret the input signals transmitted on the signal channels. Due to the chip to chip process variation during the semiconductor fabrication, the first current reference obtained from the first BandGap reference circuit 21 may differ from the second reference obtained from the second BandGap reference circuit 31. The aforementioned current references' inconsistencies will cause wrong signal interpretation at the receiver and generate a wrong output signal that will affect the accuracy of the receiver.
Therefore, there is a need for an improved interface receiver featuring a process insensitive common mode current extraction and the method extract the DC component of a clock signal as a common mode current for all clock and data signals.